MPW Design Rules


On this page you will find all of the technical information and design rules relating to our MPW service. If your requirements differ from our MPW service offerings, we can also provide bespoke fabrication runs. Contact This email address is being protected from spambots. You need JavaScript enabled to view it. for a quote.


LIVE: Seventh Call Design Rules

CORNERSTONE users are invited to submit designs to the seventh call. The platform is 340 nm Si / 2 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 2 silicon etches defined using DUV projection lithography with etch depths of 140 nm (grating couplers) and 340 nm (strip waveguides), and in addition, a high resolution silicon etch defined using e-beam lithography with an etch depth of 340 nm (photonic crystals) and minimum feature size of 100 nm.

This call is a result of user feedback informing us of the high demand for high resolution etch layers.

Once again, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a copy of the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, the CORNERSTONE PDK is free of charge if you already have a valid IPKISS license.  

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:

Design area: 11.47 mm x 4.9 mm = £5,000.

Design area: 5.5 mm x 4.9 mm = £3,500.

The mask submission deadline is Friday 25th May 2018.

For more information, full design rules and quick reference design rules, please download the CORNERSTONE 7th Call Design Rules documents and the .GDSII template files.

For any queries, including questions on bespoke processing i.e. custom etch depths etc., please contact This email address is being protected from spambots. You need JavaScript enabled to view it.


Archive: Sixth Call Design Rules

CORNERSTONE users are invited to submit designs to the sixth call. The platform is 220 nm Si / 2 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 3 silicon etches of 70 nm (grating couplers), 120 nm (rib waveguides) and 220 nm (strip waveguides). In addition, there will be two layers for metal heaters (heater filaments and heater contact pads).

For the first time, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a quote for the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, if you already have a valid license, the PDK can be accessed free of charge.

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following options:

Design area: 11.47 mm x 4.9 mm - £10,000.

Design area: 5.5 mm x 4.9 mm - £7,000.

The mask submission deadline is Friday 6th April 2018.

For more information, full design rules and quick reference design rules, please download the CORNERSTONE 6th Call Design Rules documents and the .GDSII template files.

For any queries, including questions on bespoke processing i.e. custom etch depths etc., please contact This email address is being protected from spambots. You need JavaScript enabled to view it.


Archive: Fifth Call Design Rules

CORNERSTONE users are invited to submit designs to the fifth call. The platform is 340 nm Si / 2 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 3 silicon etches of 140 nm (grating couplers), 240 nm (rib waveguides) and 340 nm (strip waveguides). In addition, there will be a 1 µm top cladding SiO2 layer.

The service is free of charge for UK academia. The cost for non-UK academia is £5,000 for a design space of 11.47 mm x 4.9 mm, or £3,500 for a design space of 5.5 mm x 4.9 mm.

The mask submission deadline is Friday 12th January 2018.

For more information, full design rules and quick reference design rules, please download the CORNERSTONE 5th Call Design Rules documents and the .GDSII template file. 

For any queries, including questions on bespoke processing i.e. custom etch depths etc., please contact This email address is being protected from spambots. You need JavaScript enabled to view it.


Archive: Fourth Call Design Rules (Active Devices)

CORNERSTONE users are invited to submit mask designs to the fourth call for active device fabrication. This service is offered free of charge to UK research institutions (funded by EPSRC), but non-UK submissions are also welcomed for a charge of £35,000. Due to popular demand, we are also offering a reduced design space of 5.5 mm x 4.9 mm for a discounted charge of £20,000.

The platform for this call is 220 nm Silicon-on-Insulator (SOI) with 3 Si etch depths of 70 nm, 120 nm and 220 nm; 4 Si implants for active device fabrication; a single metal layer for ohmic Si contacts; and 2 metal layers for heaters.

The deadline for mask submission is Friday 1st December 2017.

For more information, full design rules and quick reference design rules, please download the CORNERSTONE 4th Call Design Rules documents and the .GDSII template file.

For any queries, including questions on bespoke processing i.e. custom implants, custom etch depths etc., please contact This email address is being protected from spambots. You need JavaScript enabled to view it.


 Archive: Third Call Design Rules

CORNERSTONE users are invited to submit mask designs to the third call. This service is offered free of charge to UK institutions, but non-UK submissions are also welcomed for a small charge: please contact This email address is being protected from spambots. You need JavaScript enabled to view it. for pricing details.

The platform for this call is 500 nm Silicon-on-Insulator (SOI) with two Si etch depths of 160 nm and 500 nm.

The deadline for mask submission is Friday 28th July 2017. For more information and full design rules, please download the design rules document and .GDSII template file.

For any queries, please contact This email address is being protected from spambots. You need JavaScript enabled to view it.


Archive: Second Call Design Rules

Research institutes are invited to submit designs to the second CORNERSTONE call. This service is offered free of charge to UK institutions, but non-UK submissions are also welcomed for a small charge: please contact This email address is being protected from spambots. You need JavaScript enabled to view it. for pricing details.

The platform for this call is 220 nm Silicon-on-Insulator (SOI) with two Si etch depths of 70 nm and 220 nm. There is also the option of metal heaters.

The deadline for mask submission is Friday 30 June 2017. For more information and full design rules, please download CORNERSTONE 2nd Call Design Rules document and .GDSII template file.

For any queries, please contact This email address is being protected from spambots. You need JavaScript enabled to view it.


Archive: Second Call Training Slides

The CORNERSTONE project has published some training slides for those who would like more assistance with the design rules, and those who are new to mask design, and silicon photonics fabrication. The slides can be downloaded here


Archive: First Call Design Rules

The design rules from the CORNERSTONE first call are available here for your reference. Samples were shipped on 8th May 2017, to arrive before the 10th May 2017 deadline.