CORNERSTONE Multi Project Wafer Run 9 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 9 on the 500 nm Si / 3 µm BOX SOI platform have been announced. We will offer 2 Si etch processes: 1) a shallow Si etch of 160 nm (grating couplers), and 2) a partial Si etch of 300 nm (rib waveguides). We will also offer a 1 µm thick silicon dioxide top cladding layer.

Once again, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a copy of the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, the CORNERSTONE PDK is free of charge if you already have a valid IPKISS license.  

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:

Design area: 11.47 mm x 4.9 mm = £5,000.

Design area: 5.5 mm x 4.9 mm = £3,500.

The full design rules and .gds mask template can be found here.

The mask submission deadline is Friday 30th November 2018.

For more information on future calls, visit the Schedule & Cost page.

CORNERSTONE Multi Project Wafer Run 8 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 8 on the 220 nm Si / 2 µm BOX SOI platform have been announced. We will offer 2 Si etch processes: 1) a shallow Si etch of 70 nm (grating couplers), and 2) a partial Si etch of 120 nm (rib waveguides). We will also offer a 1 µm thick silicon dioxide top cladding layer.

This call is intended as a test bed for the next active device call on this platform, later in the year.

Once again, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a copy of the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, the CORNERSTONE PDK is free of charge if you already have a valid IPKISS license.  

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:

Design area: 11.47 mm x 4.9 mm = £5,000.

Design area: 5.5 mm x 4.9 mm = £3,500.

The full design rules and .gds mask template can be found here.

The mask submission deadline is Friday 31st August 2018.

For more information on future calls, visit the Schedule & Cost page.

Visit the CORNERSTONE Stand at PIC International Conference

We invite you to visit us at the CORNERSTONE exhibition stand at the upcoming PIC International Conference in Brussels, Belgium on 10-11 April. One lucky guest will be given the opportunity to access an upcoming “Passives with Heaters” call for FREE. To enter the free draw, place your business card in the bowl at our exhibition stand. By doing so, you will also be kept up to date with all future CORNERSTONE MPW calls.

In addition, Professor Graham Reed will be giving a talk at 11:05 on Wednesday 11th April to give more information on the CORNERSTONE project.

The PIC website contains more information: www.picinternational.net

CORNERSTONE Multi Project Wafer Run 7 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 7 on the 340 nm Si / 2 µm BOX SOI platform have been announced. We will offer 3 Si etch processes: 1) a shallow Si etch of 140 nm (grating couplers), 2) a full 340 nm etch to the BOX layer (strip waveguides), and 3) a high resolution full 340 nm etch to the BOX layer (photonic crystals) with a minimum feature size of 100 nm.

This call is a result of user feedback informing us of the high demand for high resolution etch layers.

Once again, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a copy of the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, the CORNERSTONE PDK is free of charge if you already have a valid IPKISS license.  

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:

Design area: 11.47 mm x 4.9 mm = £5,000.

Design area: 5.5 mm x 4.9 mm = £3,500.

The full design rules and .gds mask template can be found here.

The mask submission deadline is Friday 25th May 2018.

For more information on future calls, visit the Schedule & Cost page.

CORNERSTONE Multi Project Wafer Run 6 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 6 on the 220 nm Si / 2 µm BOX SOI platform have been announced. We will offer 3 Si etch processes: 1) a shallow Si etch of 70 nm (grating couplers), 2) an intermediate Si etch of 120 nm (rib waveguides), and 3) a continuation Si etch of a further 100 nm to the BOX layer (strip waveguides). In addition, we will offer two layers for metal heaters (heater filaments and heater contact pads).

For the first time, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a quote for the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, if you already have a valid license, the PDK can be accessed free of charge.

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following options:

Design area: 11.47 mm x 4.9 mm - £10,000.

Design area: 5.5 mm x 4.9 mm - £7,000.

The full design rules and .gds mask template can be found here.

The mask submission deadline is Friday 6th April 2018.

For more information on future calls, visit the Schedule & Cost page.

Research Developed Using CORNERSTONE Published in Nature Communications

A multifunctional silicon photonics integrated circuit that can be programmed to perform a variety of different functions has been developed by researchers from Spain and the UK. The chip was fabricated within the framework of the CORNERSTONE project.

This is “the first photonic integrated chip that enables multiple functionalities by employing a single common architecture”.

The results have been published in Nature Communications.

Reference: Daniel Pérez, Ivana Gasulla, Lee Crudgington, David J. Thomson, Ali Z. Khokhar, Ke Li, Wei Cao, Goran Z. Mashanovich & José Capmany. Multipurpose silicon photonics signal processor core. Nature Communications 8. doi:10.1038/s41467-017-00714-1.