CORNERSTONE Multi Project Wafer Run 2 Announced
The design rules for CORNERSTONE multi project wafer (MPW) run 2 have been announced. The platform is 220 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 2 silicon etches of 70 nm (grating couplers) and 220 nm (strip waveguides), with the option of heaters.
More information on this run can be found here.
The mask submission deadline is Friday 30th June.