CORNERSTONE Multi Project Wafer Run 5 Announced
The design rules for CORNERSTONE multi project wafer (MPW) run 5 have been announced. The platform is 340 nm Si / 2 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 3 silicon etches of 140 nm (grating couplers), 240 nm (rib waveguides) and 340 nm (strip waveguides). In addition, there will be a 1 µm top cladding SiO2 layer.
The service is free of charge for UK academia. The cost for non-UK academia is £5,000 for a design space of 11.47 mm x 4.9 mm, or £3,500 for a design space of 5.5 mm x 4.9 mm.
More information on this run can be found here.
The mask submission deadline is Friday 12th January 2018.