CORNERSTONE Multi Project Wafer Run 4 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 4 have been announced. There will be:

  • 3 Si etch processes:

1) a shallow Si etch of 70 nm (grating couplers),

2) an intermediate Si etch of 120 nm (rib waveguides), and

3) a continuation Si etch of a further 100 nm to the BOX layer (strip waveguides).

  • 4 Si implants for active device fabrication, as well as a single metal layer for ohmic Si contacts, on top of a 1 μm thick SiO2 top cladding layer.
  • Metal heaters.

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run for a charge of £35,000. Due to popular demand, we are also offering a reduced design space of 5.5 mm x 4.9 mm for a discounted cost of £20,000.

More information on can be found here.

The mask submission deadline is Friday 1st December 2017.

CORNERSTONE Multi Project Wafer Run 3 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 3 have been announced. The platform is 500 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 2 silicon etches of 160 nm (grating couplers) and 500 nm (strip waveguides).

More information on this run can be found here.

The mask submission deadline is Friday 28th July.

CORNERSTONE Second Call Training Course Released

The training course for the CORNERSTONE second call has been published. This course is intended for users who are new to mask design, or for those who want to find out more details about the design rules, fabrication process or submission process.

The training course slides can be downloaded from here.

The mask submission deadline for the second call is Friday 30th June.

CORNERSTONE Multi Project Wafer Run 2 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 2 have been announced. The platform is 220 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 2 silicon etches of 70 nm (grating couplers) and 220 nm (strip waveguides), with the option of heaters.

More information on this run can be found here.

The mask submission deadline is Friday 30th June.

Multi Project Wafer Run 1 Chips Shipped

Chips from the multi project wafer (MPW) run 1 were shipped to CORNERSTONE users on Monday 8th May to arrive on the specified delivery date of 10th May.

Any feedback from users would be greatly appreciated. Send comments to This email address is being protected from spambots. You need JavaScript enabled to view it..

Fabrication Underway on CORNERSTONE Multi Project Wafer Run 1

Fabrication at the University of Glasgow and the University of Southampton is underway for the inaugural CORNERSTONE multi project wafer (MPW) run. The process will be carried out on a 220 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI) platform, and involves 2 silicon etches of 70 nm (grating couplers) and 220 nm (strip waveguides).

More information on this run can be found here.

The delivery date for these devices is Wednesday 10th May.

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