Cornerstone

Design submission form

Please fill out this form prior to submitting your .GDSII file.

CORNERSTONE MPW Mask Submission Form

First Name*

Last Name*

Email address*

Organisation*

Phone Number*

Shipping address*

Which MPW call are you submitting to?*

Do you require CORNERSTONE to bias your designs?

What is the application of your designs?*

Do your designs contain any optical switches?*

Are your designs for quantum cryptography or QKD?*

Are your designs for analogue or digital signals?*

What is the TRL level of your work?*

TRL definition

Will you require heaters?*

Who is the end user of the dies?*

What is the end use of the dies?*

Do you require a top cladding SiO2 layer?*

What is the name of your GDS file?*

What is the name of the top cell in your GDS file?*

For Suspended-Si only: CORNERSTONE to suspend?

Do you have any other comments?

Please upload your Purchase Order (PO)<span style='color:red;'>*</span>

File(s) size limit is 20MB.

I have read, understood & met the design rules*

I accept the CORNERSTONE Terms & Conditions*

CORNERSTONE T's & C's

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CORNERSTONE brings the future closer by turning your ideas into reality. We are an open source, license free Silicon Photonics rapid prototyping foundry based in the UK. Our prototyping platforms utilise industrially-compatible deep-UV projection lithography to enable seamless scaling-up of production volumes, whilst also retaining device level innovation capability using high-resolution e-beam lithography and versatility in our process flows. This process flexibility and open source model is what differentiates CORNERSTONE from other foundries.

We offer a wide range of Silicon Photonics platforms including 3 different silicon-on-insulator platforms and a 300nm thick silicon nitride platform, as well as suspended-silicon and 3 µm thick germanium-on-silicon platforms to support emerging mid-infrared applications such as sensing. All of our platforms are available via scheduled multi-project-wafer runs or bespoke fabrication batches available on-demand.

Our diverse team are part of the Silicon Photonics groups at the Universities of Southampton and Glasgow, with several decades of experience in the field. We pride ourselves on our customer service and our ability to support researchers at all stages of their career.

202007 - CORNERSTONE Silicon Photonics Capabilities

The IPKISS Integrated Photonics Design Platform

Photonic Integrated Circuit (PIC) designers need full control of their design framework to make sure that what they fabricate matches exactly how they designed it. In addition, they need to be able to re-use and distribute their design work in a hierarchical framework that saves time and improves reliability.

Validated over > 500 designs.
A worldwide design community counting several Fortune-500 players

Learn more about the IPKISS design platform: www.lucedaphotonics.com/en

Move the edges in PIC PDK Building

Avoid the hassle of having to combine PDKs from different vendors. Circuit level design and simulation, layout and device CAD are enabled from one single quality-controlled PDK.

Luceda has a dedicated team focused entirely on releasing and supporting PDKs.

Python based PDKs: Full flexibility to optimize layout and yield.
Smart Physical Simulation models seamlessly link Layout, Physical simulation and Circuit simulation: Physical simulation strategy part of the parameterized PDK model.
OpenAccess and iPDK standards
Deploy your PDKs to different EDA vendors
Quality assurance tools will give you a master view over the PDK development: Regression testing and sign off at version updates.

Learn more about the CORNERSTONE PDK: www.lucedaphotonics.com/en/pdk-and-fab-support#CORNERSTONE

Useful links

Get more information: www.lucedaphotonics.com/en/contact

Order the tools:

European Academia: www.europractice.stfc.ac.uk/software/luceda_photonics.html

Industry: www.lucedaphotonics.com/en/contact

Legal

On this page you can download our standard Non-Disclosure Agreement (NDA). If you have any queries, contact This email address is being protected from spambots. You need JavaScript enabled to view it..

Non-Disclosure Agreement (NDA)

Note: An NDA is optional. CORNERSTONE does not require an NDA to be signed.

If you intend to submit commercially sensitive designs to CORNERSTONE then both parties are required to sign an NDA. This MUST be stated at the Sign-Up stage, at least 4 weeks before the mask submission deadline, so that the necessary procedures can be initiated. For an expedited process, it is essential that the NDA is accepted in its current form, which you can download below.

CORNERSTONE Optional NDA - June 2020

If any changes are required, we cannot guarantee that they will be complete before the mask submission deadline.

There are no deadlines for completion of the NDA (if applicable) for bespoke fabrication batches.

Process Design Kit (PDK)

The CORNERSTONE platform has a number of open source standard components available for use for each of its platforms.

The document below details the standard device dimensions for each platform, as well as measured performance data:

CORNERSTONE SOI Standard Components Library - Feb 2022

CORNERSTONE SiN Standard Components Library - Feb 2022

CORNERSTONE Suspended-Si Standard Components Library - Feb 2022

We have a process design kit available in Luceda Photonics' IPKISS platform.

Alternatively, the standard components are available in .gdsII format:

CORNERSTONE GDSII Template_All Platforms_Apr 2022.

The design rules from the most recent MPW call for each platform can also be downloaded below. Be sure to check the live design rule documents for the call you intend to submit to in case there have been any updates to the design rules.

220nm SOI passives:

CORNERSTONE 28th Call - Design Rules

220nm SOI actives:

CORNERSTONE 22nd Call - Design Rules

340nm SOI passives:

CORNERSTONE 27th Call - Design Rules

500nm SOI passives:

CORNERSTONE 29th Call - Design Rules

300nm SiN:

CORNERSTONE Silicon Nitride MPW 3 - Design Rules

Suspended-Si:

CORNERSTONE Suspended Si MPW 2 - Design Rules