Cornerstone

CORNERSTONE 2 updates

Our open access model differentiates us from other foundries.

Our prototyping platform uses industry-compatible, deep-UV projection lithography meaning you can seamlessly scale up production volumes via your favourite commercial foundry.
The platform retains device-level innovation capability and flexibility in its process flows, making it the perfect choice for researchers who want to try out innovative designs or evaluate new photonic circuits.

We currently offer:
  • 3 different silicon-on-insulator platforms: 220nm, 340nm and 500nm Si
  • 1 silicon nitride platform: 300n
  • Bespoke fabrication batches on request
  • DUV Lithography
  • Coming soon
  • 5 new exciting new silicon based platforms, based on demand from users, all of which will be available soon

Find out more

We offer:

  • 3 different silicon-on-insulator platforms: 220nm, 340nm and 500nm Si
  • 1 silicon nitride platform: 300n
  • Bespoke fabrication batches on request
  • DUV Lithography
  • Coming soon
  • 5 new exciting new silicon based platforms, based on demand from users, all of which will be available soon

Find out more

Coming soon

Mask upload form

Please fill out this form prior to submitting your .GDSII file. Once this form is completed, you will receive login details to the mask uploading module within 24 hours, where you can upload your file to be accessed by the CORNERSTONE team.

CORNERSTONE 2

The CORNERSTONE team have won ~£1.5M in funding from the UK Engineering and Physical Sciences Research Centre (EPSRC) to expand the capabilities offered by the service.

In CORNERSTONE 2, the team will develop 6 new silicon based technology platforms for researchers to design their photonic integrated circuits. The platforms extend the supported wavelength range into both the visible wavelengths and mid-infrared wavelengths, enabling a plethora of applications including LIDAR, lab-on-a-chip sensing and more. The 6 new platforms comprise:

  1. Flip-chip bonding of electronic circuits to photonics
  2. Pick and place of laser dies to facilitate on-chip light sources for multiple applications
  3. A high confinement Silicon Nitride photonics platform with thickness up to 1 µm
  4. An undercut Silicon Photonics platform to facilitate photonics circuits that operate at wavelengths up to 4 µm
  5. A Germanium-on-Silicon platform for photonics circuits that operate at wavelengths up to 12 µm
  6. Deep-UV projection lithography service

More information about the platforms can be found in the file below.

CORNERSTONE 2 is a collaborative project between teams led by Professor Graham Reed at the University of Southampton and Professor Marc Sorel at the University of Glasgow. The Glasgow team will be responsible for integrating light sources onto silicon photonics chips, a major step in the commercialisation of silicon photonics. The Southampton team will be responsible for the remaining platforms on 200 mm substrates, utilising the deep-UV projection lithography capability installed in the first CORNERSTONE project.

The project PI, Professor Graham Reed, Deputy Director of the ORC and Professor of Silicon Photonics said: “I'm delighted that the EPSRC are supporting the expansion of CORNERSTONE. I believe that it will enable researchers to have significant impact in a variety of silicon-based platforms.”

Professor Harold Chong, project co-investigator and Professor of Electronic Engineering in the Electronics and Computer Science department said: “The flexibility of the processes and the variety of the platforms available in CORNERSTONE 2 gives researchers numerous options when designing optoelectronics devices and systems.”

The project will officially commence on 1st March 2020 and run for 2-years. UK academics will have the opportunity to access the new platforms free-of-charge for the final 6 months of the project, with access opportunities for international researchers available for a charge during this final 6 month period and beyond. Throughout the CORNERSTONE 2 project, the team will be consulting the community to determine if they would like to see CORNERSTONE become an EPSRC National Research Facility (NRF).

The current SOI capability will continue to operate as it has done for the previous years. All users will be charged at the rates advertised on the Schedule & Cost page.

If you are interested in any of the above platforms, please email This email address is being protected from spambots. You need JavaScript enabled to view it. to find out more.

Homepage Intro

CORNERSTONE is a license free, open source Silicon Photonics rapid prototyping foundry based in the UK. Our open access and license free model differentiates us from other foundries. Our prototyping platform uses industry-compatible, deep-UV  projection lithography meaning you can seamlessly scale up production volumes via your favourite commercial foundry. The platform retains device-level innovation capability and flexibility in its process flows, making it the perfect choice for researchers who want to try out innovative designs or evaluate new photonic circuits.

CORNERSTONE offers 3 different silicon-on-insulator platforms and a silicon nitride platform via a multi-project-wafer service. We will soon be launching 4 exciting new silicon based platforms based on demand from users, all of which will be available over the next year, find out more!

 The capabilities of the Silicon Photonics Group at the University of Southampton can be downloaded below.

Legal

On this page you can download our standard Non-Disclosure Agreement (NDA) and Terms & Conditions. If you have any queries, contact This email address is being protected from spambots. You need JavaScript enabled to view it..

Non-Disclosure Agreement (NDA)

Note: An NDA is optional. CORNERSTONE does not require an NDA to be signed.

If you intend to submit commercially sensitive designs to CORNERSTONE then both parties are required to sign an NDA. This MUST be stated at the Expression of Interest (EoI) stage, at least 6 weeks before the mask submission deadline, so that the necessary procedures can be initiated. For an expedited process, it is essential that the NDA is accepted in its current form, which you can download below.

If any changes are required, we cannot guarantee that they will be complete before the mask submission deadline.

There are no deadlines for completion of the NDA (if applicable) for bespoke fabrication batches.


Terms & Conditions

Note: All CORNERSTONE partners MUST agree to the Terms & Conditions when submitting a mask design.

The CORNERSTONE Terms & Conditions can be downloaded below. 

The IPKISS Integrated Photonics Design Platform

Photonic Integrated Circuit (PIC) designers need full control of their design framework to make sure that what they fabricate matches exactly how they designed it. In addition, they need to be able to re-use and distribute their design work in a hierarchical framework that saves time and improves reliability.

  • Validated over > 500 designs.
  • A worldwide design community counting several Fortune-500 players

Learn more about the IPKISS design platform: www.lucedaphotonics.com/en


Move the edges in PIC PDK Building

Avoid the hassle of having to combine PDKs from different vendors.  Circuit level design and simulation, layout and device CAD are enabled from one single quality-controlled PDK.

Luceda has a dedicated team focused entirely on releasing and supporting PDKs.

  • Python based PDKs: Full flexibility to optimize layout and yield.
  • Smart Physical Simulation models seamlessly link Layout, Physical simulation and Circuit simulation: Physical simulation strategy part of the parameterized PDK model.
  • OpenAccess and iPDK standards
  • Deploy your PDKs to different EDA vendors
  • Quality assurance tools will give you a master view over the PDK development: Regression testing and sign off at version updates.

Learn more about the CORNERSTONE PDK: www.lucedaphotonics.com/en/pdk-and-fab-support#CORNERSTONE


Useful links

Get more information: www.lucedaphotonics.com/en/contact

Order the tools:

European Academia: www.europractice.stfc.ac.uk/software/luceda_photonics.html

Industry: www.lucedaphotonics.com/en/contact

 

 

Archived MPW Design Rules

On this page you will find all of the technical information and design rules relating to our previous calls. This is intended to give an overview of typical design rules for each platform. However, this information is subject to change for future calls.

If you have any queries, or your requirements differ from our MPW service offerings, contact This email address is being protected from spambots. You need JavaScript enabled to view it..

 

Archive: Twenty-Fourth Call Design Rules (500 nm SOI passive devices with heaters)

The design rules for the twenty-fourth call can be downloaded below, for your reference.


Archive: Twenty-Third Call Design Rules (220 nm SOI passive devices with heaters)

The design rules for the twenty-third call can be downloaded below, for your reference.


Archive: Twenty-Second Call Design Rules (220 nm SOI active devices)

The design rules for the twenty-second call can be downloaded below, for your reference.


Archive: Twenty-First Call Design Rules (340 nm SOI passive devices with heaters)

The design rules for the twenty-first call can be downloaded below, for your reference. 


Archive: Twentieth Call Design Rules (220 nm SOI passive devices with heaters)

The design rules for the twentieth call can be downloaded below, for your reference.


Archive: Nineteenth Call Design Rules (500 nm SOI passive devices with heaters)

The design rules for the nineteenth call can be downloaded below, for your reference.


Archive: Eighteenth Call Design Rules (220 nm SOI passive devices with heaters)

The design rules for the eighteenth call can be downloaded below, for your reference.


Archive: Seventeenth Call Design Rules (220 nm SOI active devices)

The design rules for the seventeenth call can be downloaded below, for your reference.


Archive: Sixteenth Call Design Rules (340 nm SOI passive devices with heaters)

The design rules for the sixteenth call can be downloaded below, for your reference.


Archive: Fifteenth Call Design Rules (220 nm SOI passive devices with heaters)

The design rules for the fifteenth call can be downloaded below, for your reference.


Archive: Fourteenth Call Design Rules (500 nm SOI passive devices with heaters)

The design rules for the fourteenth call can be downloaded below, for your reference.


Archive: Thirteenth Call Design Rules (220 nm SOI passive devices with heaters)

The design rules for the thirteenth call can be downloaded below, for your reference.


Archive: Twelfth Call Design Rules (340 nm SOI passive devices with heaters)

The design rules for the twelfth call can be downloaded below, for your reference.


Archive: Eleventh Call Design Rules (220 nm SOI active devices)

The design rules for the eleventh call can be downloaded below, for your reference.


Archive: Tenth Call Design Rules (220 nm SOI passive devices with heaters)

The design rules for the tenth call can be downloaded below, for your reference.


Archive: Ninth Call Design Rules (500 nm SOI passive devices)

The design rules for the ninth call can be downloaded below, for your reference.


Archive: Eighth Call Design Rules (220 nm SOI passive devices)

The design rules for the eighth call can be downloaded below, for your reference.


Archive: Seventh Call Design Rules (340 nm SOI passive devices with high resolution layer)

The design rules for the seventh call can be downloaded below, for your reference.


Archive: Sixth Call Design Rules (220 nm SOI passive devices with heaters)

The design rules for the sixth call can be downloaded below, for your reference.


Archive: Fifth Call Design Rules (340 nm SOI passive devices)

The design rules for the fifth call can be downloaded below, for your reference.


Archive: Fourth Call Design Rules (220 nm SOI active devices)

 The design rules for the fourth call can be downloaded below, for your reference.


 Archive: Third Call Design Rules (500 nm SOI passive devices)

 The design rules for the third call can be downloaded below, for your reference.


Archive: Second Call Design Rules (220 nm SOI passives devices with heaters)

 The design rules for the second call can be downloaded below, for your reference.


Archive: Second Call Training Slides

The CORNERSTONE project has published some training slides for those who would like more assistance with the design rules, and those who are new to mask design, and silicon photonics fabrication. The slides can be downloaded here


Archive: First Call Design Rules (220 nm SOI passive devices)

The design rules from the CORNERSTONE first call are available here for your reference. Samples were shipped on 8th May 2017, to arrive before the 10th May 2017 deadline.

Process Design Kit (PDK)

The CORNERSTONE platform has a number of open source standard components available for use for each of its standard SOI platforms.

The document below details the standard device dimensions for each platform, as well as measured performance data:

We have a process design kit available in Luceda Photonics' IPKISS platform.

Alternatively, the standard components are available in .gdsII format: