PIC Bootcamp ADVANCED: PIC design using Lumerical and Synopsys Optocompiler

This advanced course provides practical training in the design and simulation of photonic devices and photonic integrated circuits (PICs) using Ansys Lumerical and Synopsys OptoCompiler.

Delegates will learn the underlying theory of key photonic components and circuits, then apply it through guided design and simulation exercises using industry-standard tools and the CORNERSTONE process design kit (PDK).

This advanced course provides practical training in the design and simulation of photonic devices and photonic integrated circuits (PICs) using Ansys Lumerical and Synopsys OptoCompiler.

This course was developed with funding from the CORNERSTONE Photonics Innovation Centre programme (EP/Z531066/1) and is offered at a heavily discounted rate exclusively to eligible delegates from UK academia and other EPSRC-eligible organisations, and qualifying UK start-ups. Please contact cornerstone@soton.ac.uk with any eligibility queries.

What will you gain?

  • An understanding of where PICs can be deployed, their advantages and limitations.​
  • A high-level comprehension of PIC components and how they can form larger circuits.​
  • Industrial level skills in PIC design through hands-on guided lesson plans

Pre-requisites:

Delegates should have background experience in PICs and their applications. Some previous experience of using design and simulation software would be beneficial.

Course Schedule

DAY 1

  • Introduction to photonics and design flows
  • Principles of photonic waveguides and optical mode design
  • Exercises on cross-sectional design and simulation in Lumerical

DAY 2

  • Electromagnetic propagation simulation theory and exercises
  • Physical effects theory and exercises in the DEVICE Multi-Physics Utility
  • Theory and exercises on creating a custom cell with the Compact Model Library Compiler

DAY 3

  • The OptoCompiler environment, Schematic Editor and design exercises
  • PrimeWave circuit simulation, and CORNERSTONE PIC design exercises

DAY 4

  • Mask layout design theory and excersises
  • Circuit verification DRC and LVS theory with exercises

Fees

  • Standard Rate: £350

Date: 2nd November to 5th November 2025

Location: STFC Rutherford Appleton Laboratory, Didcot, Oxfordshire, UK